A low level of dislocation defects is important in a wide variety of semiconductor devices and processes. Dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties. Dislocation defects can arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material (heterostructures) due to different crystalline lattice sizes of the two materials. Misfit dislocations form at the mismatched interface to relieve the misfit strain. Many misfit dislocations have vertical components, termed threading segments, which terminate at the surface. These threading segments continue through all subsequent layers added. Dislocation defects can also arise in the epitaxial growth of the same material as the substrate (homostructures) where the substrate itself contains dislocations. Some of the dislocations replicate as threading dislocations in the epitaxially grown material. Such dislocations in the active regions of semiconductor devices such as diodes, lasers and transistors, seriously degrade performance.
To avoid dislocation problems, most semiconductor heterostructure devices have been limited to semiconductor layers that have very closely lattice-matched crystal structures. Typically the lattice mismatch is within 0.1%. In such devices a thin layer is epitaxially grown on a mildly lattice mismatched substrate. So long as the thickness of the epitaxial layer is kept below a critical thickness for defect formation, the substrate acts as a template for growth of the epitaxial layer which elastically conforms to the substrate template. While lattice matching and near matching eliminates dislocations in a number of structures, there are relatively few lattice-matched systems with large energy band offsets, limiting the design options for new devices.
There is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than present technology will allow. For example, it has long been recognized that gallium arsenide grown on silicon substrates would permit a variety of new optoelectronic devices marrying the electronic processing technology of silicon VLSI circuits with the optical component technology available in gallium arsenide. See, for example, Choi et al, "Monolithic Integration of Si MOSFET's and GaAs MESFET's", IEEE Electron Device Letters, Vol. EDL-7, No. 4, April 1986. Highly advantageous results of such a marriage include high speed gallium arsenide circuits combined with complex silicon VLSI circuits and gallium arsenide optoelectronic interface units to replace wire interconnects between silicon VLSI circuits. Progress has been made in integrating gallium arsenide and silicon devices. See, for example, Choi et al, "Monolithic Integration of GaAs/AlGaAs Double-Heterostructure LED's and Si MOSFET's" IEEE Electron Device Letters, Vol. EDL-7, No. 9, September 1986; Shichijo et al, "Co-Integration of GaAs MESFET and Si CMOS Circuits", IEEE Electron Device Letters, Vol. 9, No. 9, September 1988. However, despite the widely recognized potential advantages of such combined structures and substantial efforts to develop them, their practical utility has been limited by high defect densities in gallium arsenide layers grown on silicon substrates. See, for example, Choi et al, "Monolithic Integration of GaAs/AlGaAs LED and Si Driver Circuit", IEEE Electron Device Letters, Vol. 9, No. 10, October 1988 (p. 513). Thus while basic techniques are known for integrating gallium arsenide and silicon devices, there exists a need for producing gallium arsenide layers having a low density of dislocation defects.
There is also considerable interest in growing low defect density gallium arsenide surfaces irrespective of the type of substrate. Gallium arsenide is prone to dislocation defects; and, as a consequence, devices grown on gallium arsenide substrates have a notoriously low yield.